FPGA‐based Implementation of Signal Processing Systems, Second Edition

This chapter gives some insight into the tools and their capabilities from a synthesis point of view and also because they would appear to be closely linked to FPGAs. In particular, there is an interest in how much of the architectural mapping has now been automated. The chapter discusses high-level synthesis (HLS) and describes the problems of using C to model hardware. A C-based approach, specifically Xilinx Vivado HLS tools, is described, followed by an OpenCL alternative, Altera's SDK for OpenCL. A number of other HLS tools have been developed, including C-based synthesis tools both in the commercial (Catapult and Impulse-C) and academic (GAUT, CAL and LegUp) domain with some focus on FPGA, and higher-level tools such as dataflow-based synthesis tools. The tools that have been chosen and described in the chapter are the ones specifically linked to FPGAs.