FPGA‐based Implementation of Signal Processing Systems, Second Edition

This chapter covers the evolution of reusable design processes, concentrating on FPGA-based IP core generation. It describes IP core integration and covers current FPGA-based IP cores. Dedicated hardware functionality has been included in many FPGA families to support fixed-point addition/subtraction and multiplication and is supported in high-level synthesis tools. As the level of abstraction within the core building blocks in designs increases, the role of the designer moves toward that of a system integrator, particularly with development using current FPGA devices enabling full system functionality on a single device. The chapter covers the development of parameterizable IP cores for DSP functions. The starting point for the hardware design of a mathematical component may be the SFG representation of the algorithm. A graphical depiction of the algorithm shows the components required within the design and their interdependence. Many of the IP designs applied for ASIC design can be expanded for FPGA implementations.