Advanced Model-Based FPGA Accelerator Design
Abstract
Architectural synthesis of SFG models is a powerful approach to the design of high-throughput custom circuit accelerators for FPGA. This chapter addresses dataflow modeling and synthesis approaches for advanced accelerator architectures which fall into either of two classes. The first is that of multidimensional accelerators: those which operate on complex multidimensional data objects, or multiple channels of data. The second focuses on accelerators with an issue largely ignored by the SFG synthesis techniques, where it is a heavy demand for high- capacity memory resource which must be accessed at a high rate. The chapter describes the dataflow modeling of DSP systems. It covers synchronous dataflow (SDF), cyclo-static dataflow (CSDF) and multidimensional synchronous dataflow (MSDF). MSDF provides an elegant solution to multidimensional scheduling problems in SDF graphs. The chapter addresses techniques for representing, deriving and optimizing FPGA accelerators for pipelined streaming operators.
