FPGA‐based Implementation of Signal Processing Systems, Second Edition

This chapter focuses on QR-based IP core for adaptive beamforming. It first outlines the generic process and shows how it is applied to adaptive beamforming. Next, the chapter discusses how the algorithm is mapped to the architecture and shows how it is applied to the squared Givens rotations for RLS filtering. The efficient architecture design is then outlined and applied to the QR design example. The chapter continues with the discussion of retiming issues and how to include them in a generic architecture. Parametric ways of generating the control for the various QR architectures are subsequently discussed. The chapter also analyzes how latency may be accounted for within the control generation. Finally, examples are given on how control circuitry could be developed so as to scale with the architecture, while maintaining performance criteria.