FPGA‐based Implementation of Signal Processing Systems, Second Edition

The chapter covers some techniques that specifically look at mapping digital signal processing (DSP) systems onto specific field programmable gate array (FPGA) platforms. It treats the programmable logic elements in the FPGA and highlights how the LUT and dedicated adder circuitry can be used for implementing logic and DSP functionality. At circuit level much of the detailed logic analysis and synthesis work has focused on mapping functions into logic gates, but in FPGA the underlying cost function is a four- to eight-input LUT and flip-flop combination, so the goal is to map to this underlying fabric. Some simple optimizations for mapping into LUTs and efficient implementation of finite state machines (FSMs) are covered. The class of fixed coefficient filters and transforms is described with some discussion on how they can be mapped efficiently into programmable logic. Techniques called distributed arithmetic and reduced coefficient multiplier (RCM) used to implemented fixed or limited-range coefficient functions are also described.